About vSync Circuits
Synchronization failures are a common pitfall in
multiple clock domain designs. These bugs are hard to
fix, because the failures are often intermittent and hard
to catch. Fixing such bugs in FPGA may take weeks of
debugging, and they may be impossible to catch in
ASIC prior to fabrication.
vSync Circuits delivers a twofold solution to this
problem. The vGenerator tool provides the necessary
fool-proof synchronizer customized for each interface
and each clock domain crossing. The vChecker tool
verifies the complete design statically, hunting for
trouble and assessing expected reliability.
Unlike typical clock domain crossing (CDC) verification
tools, the vSync Circuits suite focuses on providing the
correct solutions, rather than merely pointing at the
problems.
The advanced abilities of vSync Circuits tool kit provide
a complete solution for multiple clock domain
ASIC/FPGA integration and CDC verification, covering
all the stages of the VLSI design flow: from the RTL
design down to GDSII/Bitsream.


VSYNC CIRCUITS LTD.
A Complete Solution for Multiple-Clock Domain SoC
Integration and Verification
NEWS
 | | Jan. 31, 2012: v2.10 was |
| | released
|
 | | Aug. 31, 2011: v2.05 was |
| | released
|
 | | May 4, 2010: vSync Circuits at |
| | ChipEx10
|